Etch stop layer system

ABSTRACT

A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si 1-x Ge x  alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than  7×10   19  cm −3  of boron or undoped Si 1-x Ge x  alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium. Furthermore, the nondegenerate doping in the Si 1-x Ge x  alloy should not affect the etch-stop behavior. The etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material. Nominally, the buffer has a linearly-changing composition with respect to thickness, from pure silicon at the substrate/buffer interface to a composition of germanium, and dopant if also present, at the buffer/etch-stop interface which can still be etched at an appreciable rate. Here, there is a strategic jump in germanium and concentration from the buffer side of the interface to the etch-stop material, such that the etch-stop layer is considerably more resistant to the etchant. This process and layer structure allows for an entire range of new materials for microelectronics. The etch-stop capabilities introduce new novel processes and structures such as relaxed SiGe alloys on Si, SiO 2 , and SiO 2 /Si. Such materials are useful for future strained Si MOSFET devices and circuits.

PRIORITY INFORMATION

[0001] This application is a continuation-in-part application of Ser.No. 09/289,514 filed April 9, 1999, which claims priority fromprovisional application Ser. No. 60/081,301 filed Apr. 10, 1999.

BACKGROUND OF THE INVENTION

[0002] The invention relates to the field of etch-stop material systemson monocrystalline silicon.

[0003] Microelectromechanical systems (MEMS) form the bridge betweenconventional microelectronics and the physical world. They serve theentire spectrum of possible applications. MEMS include such varieddevices as sensors, actuators, chemical reactors, drug delivery systems,turbines, and display technologies. At the heart of any MEMS is aphysical structure (a membrane, cantilever beam, bridge, arm, channel,or grating) that is “micromachined” from silicon or some otherelectronic material. Since MEMS are of about the same size scale and,ideally, fully integrated with associated microelectronics, naturallythey should capitalize on the same materials, processes, equipment, andtechnologies as those of the microelectronics industry. Because theprocess technology for silicon is already extensively developed for VLSIelectronics, silicon is the dominant material for micromachining.Silicon is also mechanically superior to compound semiconductormaterials and, by far, no other electronic material has been asthoroughly studied.

[0004] A wide array of micromachined silicon devices are fabricatedusing a high boron concentration “etch-stop” layer in combination withanisotropic wet etchants such as ethylenediamine and pyrocatecholaqueous solution (EDP), potassium hydroxide aqueous solution (KOH), orhydrazine (N₂H₂). Etch selectivity is defined as the preferentialetching of one material faster than another and quantified as the ratioof the faster rate to the slower rate. Selectivity is realized for boronlevels above 10¹⁹ cm⁻³, and improves as boron content increases.

[0005] It should be noted that etch stops are also used in bond andetch-back silicon on insulator (BESOI) processing for SOImicroelectronics. The etch-stop requirements differ somewhat from thoseof micromachining, e.g., physical dimensions and defects, but thefundamentals are the same. Hence, learning and development in one areaof application can and should be leveraged in the other. In particular,advances in relaxed SiGe alloys as substrates for high speed electronicssuggests that a bond-and-etch scheme for creating SiGe-on-insulatorwould be a desirable process for creating high speed and wirelesscommunications systems.

SUMMARY OF THE INVENTION

[0006] Accordingly, the invention provides a SiGe monocrystallineetch-stop material system on a monocrystalline silicon substrate. Theetch-stop material system can vary in exact composition, but is a dopedor undoped Si_(1-x)Ge_(x) alloy with x generally between 0.2 and 0.5.Across its thickness, the etch-stop material itself is uniform incomposition. The etch stop is used for micromachining by aqueousanisotropic etchants of silicon such as potassium hydroxide, sodiumhydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine(EDP), TMAH, and hydrazine. For example, a cantilever can be made ofthis etch-stop material system, then released from its substrate andsurrounding material, i.e., “micromachined”, by exposure to one of theseetchants. These solutions generally etch any silicon containing lessthan 7×10¹⁹ cm⁻³ of boron or undoped Si_(1-x)Ge_(x) alloys with x lessthan approximately 18.

[0007] Alloying silicon with moderate concentrations of germanium leadsto excellent etch selectivities, i.e., differences in etch rate versuspure undoped silicon. This is attributed to the change in energy bandstructure by the addition of germanium. Furthermore, the nondegeneratedoping in the Si_(1-x)Ge_(x) alloy should not affect the etch-stopbehavior.

[0008] The etch-stop of the invention includes the use of agraded-composition buffer between the silicon substrate and the SiGeetch-stop material. Nominally, the buffer has a linearly-changingcomposition with respect to thickness, from pure silicon at thesubstrate/buffer interface to a composition of germanium, and dopant ifalso present, at the buffer/etch-stop interface which can still beetched at an appreciable rate. Here, there is a strategic jump ingermanium and concentration from the buffer side of the interface to theetch-stop material, such that the etch-stop layer is considerably moreresistant to the etchant.

[0009] In accordance with the invention there is provided amonocrystalline etch-stop layer system for use on a monocrystaliine Sisubstrate. In one embodiment of the invention, the system includes asubstantially relaxed graded layer of Si_(1-x)Ge_(x), and a uniformetch-stop layer of substantially relaxed Si_(1-y)Ge_(y). In anotherembodiment of the invention, the system includes a substantially relaxedgraded layer of Si_(1-x)Ge_(x), a uniform etch-stop layer ofsubstantially relaxed Si_(1-y)Ge_(y), and a strainedSi_(1-x)Ge_(x)layer. In yet another embodiment of the invention, thesystem includes a substantially relaxed graded layer of Si_(1-x)Ge_(x),a uniform etch-stop layer of substantially relaxed Si_(1-y)Ge_(y), asecond etch-stop layer of strained Si_(1-z)Ge_(z), and a substantiallyrelaxed Si_(1-w)Ge_(w) layer.

[0010] In accordance with the invention there is also provided a methodof integrating device or layer. The method includes depositing asubstantially relaxed graded layer of Si_(1-x)Ge_(x) on a Si substrate;depositing a uniform etch-stop layer of substantially relaxedSi_(1-y)Ge_(y) on the graded buffer; and etching portions of thesubstrate and the graded buffer in order to release the etch-stop layer.

[0011] In accordance with another embodiment of the invention, there isprovided a method of integrating a device or layer. The method includesdepositing a substantially relaxed graded layer of Si_(1-x)Ge_(x) on aSi substrate; depositing a uniform first etch-stop layer ofsubstantially relaxed Si_(1-y)Ge_(y) on the graded buffer; depositing asecond etch-stop layer of strained Si_(1-z)Ge_(z); depositing asubstantially relaxed Si_(1-w)Ge_(w) layer; etching portions of thesubstrate and the graded buffer in order to release the first etch-stoplayer; and etching portions of the residual graded buffer in order torelease the second etch-stop Si_(1-z)Ge_(z)layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIGS. 1A-1D are functional block diagrams of exemplary epitaxialSiGe etch stop structures configured on a silicon substrate inaccordance with the invention;

[0013]FIG. 2 is a cross-sectional TEM micrograph of the structure ofFIG. 1B;

[0014]FIG. 3 is a cross-sectional TEM micrograph of the structure ofFIG. 1C;

[0015]FIG. 4 is graph of dopant concentrations of the structure of FIG.1A;

[0016]FIG. 5 is a graph of dopant concentrations of the structure ofFIG. 1D;

[0017]FIG. 6A is a graph showing the cylindrical etch results of thestructure of FIG. 1A; FIG. 6B is graph showing a magnification of theleft side of FIG. 6A;

[0018]FIG. 7 is a graph showing the cylindrical etch results of thestructure of FIG. 1D;

[0019]FIG. 8 is a graph showing the etch rates for <100> intrinsicsilicon in 34% KOH at 60° C. normalized by 18.29 μm/hr of the structuresof FIGS. 1A-1D;

[0020]FIG. 9 is a photograph of a top view of a micromachined proofmass;

[0021]FIG. 10 is a block diagram of a process for fabricating anSiGe-on-insulator structure; FIG. 11A-11F are schematic diagrams of thefabrication process for SiGeOI;

[0022]FIGS. 12A and 12B are IR transmission images of intrinsic voidsdue to particles at the bonding interface, and a demonstration ofvoid-free bonding, and crack due to Maszara surface energy test for SiGebonded to oxide prior to annealing, respectively;

[0023]FIG. 13 is a graph of oxide thickness versus oxidation time, for700° C. wet oxidation of SiGe alloys for various Ge concentration;

[0024]FIG. 14 is a graph showing the etching results using aHF:H₂O₂:CH₃COOH (1:2:3) solution, for the a test structure shown ininset diagram;

[0025]FIG. 15 is a cross-sectional TEM micrograph of a final exemplarySiGe on oxide structure; and

[0026]FIG. 16 is an atomic force microscope surface map of the remainingstrained Si layer in the SiGeOI structure, after the 30 minuteHF:H₂O₂:CH₃COOH (1:2:3) etch.

DETAILED DESCRIPTION OF THE INVENTION

[0027] In the traditional method of forming etch stops in Simicromachining or in certain SOI processes, good etch-stop results areonly obtained at very high concentrations of boron, and the dopant'seffect on the silicon crystal structure becomes vitally important.Substitution of a silicon atom site with boron, a smaller atom thansilicon, contracts the silicon lattice. As the doped lattice remainscoherent with the lattice of the undoped substrate, a biaxial “latticemismatch” stress is generated in the plane of the substrate. This stressbiaxially elongates, i.e., elastically strains, the doped material inthe same plane. As the base of a unit cell is strained, so is the heightvia Poisson distortion. Therefore, the Si:B lattice is verticallycontracted as it is horizontally expanded, leading to a smaller verticallattice constant than the equilibrium value. For thin layers of Si:B, itis energetically favorable for the material to be elastically strainedlike this, i.e., “pseudomorphic”.

[0028] As the thickness of the doped layer grows, however, the totalstrain energy per unit area of film increases proportionally, until thelayer surpasses a “critical thickness” when it is energeticallyfavorable to introduce dislocations instead of elastically straining thefilm. Dislocation loops are heterogeneously nucleated at the filmsurface or film edges and grow larger, gliding towards thesubstrate-film interface. When a loop meets the interface, the two ends(now called “threading” dislocations because they traverse the thicknessof the film) continue to travel away from each other, trailing a linedefect at the interface known as a “misfit” dislocation. The misfitdislocations accommodate the lattice-mismatch stress, relieving thehorizontal and vertical strains and restoring the in-plane andperpendicular lattice constants to the equilibrium value, i.e.,“relaxing” the material. For a low-mismatched lightly strained epitaxialfilm on a diamond cubic or zincblende substrate, a mesh of orthogonal<110> misfit dislocations is the most likely configuration because ofthe {111}<110> easy slip system for these crystal structures at elevatedtemperatures, such as those involved in diffusion and most CVDprocesses.

[0029] At high enough quantities, the effects of any dissimilar-sizedsubstitutional atom on the silicon microstructure are the same as thoseof boron. Of course, the impact depends on the relative size andconcentration of the substitutional species. Also, incorporation of alarger atom than silicon, e.g., germanium, would result in compressivestress and strain rather than a tensile situation like Si:B.

[0030] In the conventional etch stop process, extremely highconcentrations of boron are needed to achieve a high etch rateselectivity. These very high boron concentrations lead to dislocationintroduction in the thick films that are desired in many MEMSapplications. Since the p++ process is created usually through adiffusion process, there is a gradient in dislocation density and agradient in the boron concentration. Because the etch stops in the boronconcentration gradient, the thin film part typically possesses largecurvature, which is compensated for by an annealing treatment. Inaddition, the etch stop selectivity is extremely sensitive to the boronconcentration. If the concentration falls below the critical 7×10¹⁹cm⁻³, the selectivity is drastically different. Thus, since this boronconcentration is near the solubility limit, dopant concentrationfluctuations in the vertical and lateral dimensions produce low yieldsin MEMS processes. The SiGe etch stop breaks the link between dopantconcentration and etch selectivity.

[0031] Also, since the SiGe alloy is a miscible alloy system, there iscontinuous complete solubility between Si and Ge.

[0032] The theory of anisotropic etching of silicon as described bySeidel et al., J. Electrochem.

[0033] Soc. 137, pp. 3626-31 (1990), incorporated herein by reference,is widely considered the appropriate model. Although specifics likeabsolute etch rate and dissolution products may differ, the generalconcept is valid for all anisotropic etchants, as they are all aqueousalkaline solutions and the contribution of the etchant is modeled asnothing more specific than H₂O and OH⁻. Indeed, the existing literatureshows consistent behavior among the etchants.

[0034] Early work on etch rate reduction in p++ Si:B presented nohypotheses beyond empirical data. Two possible explanations for theetch-stop phenomenon were proposed: stronger bonding from the high boronconcentration or the formation of a boron-based passivation layer. Asresearch accumulated, the etch-stop theories aligned along two credibleapproaches. The electronic models assign etch-stop behavior to theaction of carriers while the passivation models directly attribute it tothe formation of a passivating oxide-based layer on the silicon surface.

[0035] Others concluded that the etch-rate decrease is sensitive to holeconcentration and not to atomic concentration of boron or stress. Theyobserved an etch rate drop that was proportional to the fourth power ofthe increase in boron concentration beyond about 3×10¹⁹ cm⁻³. Fourelectrons are required by a red-ox etching process they described,leading them to explain the etch-stop effect in p++ material as anincreased probability that the electrons are lost to Auger recombinationbecause of the higher hole concentrations.

[0036] Seidel et al. agreed with the electron recombination hypothesis.They saw the etch rate begin to fall around 2-3×10¹⁹ cm⁻³, which agreeswith the doping level for the onset of degeneracy, 2.2×10¹⁹ cm⁻³. Atdegeneracy, the Fermi level drops into the valence band and theband-bending is confined to a thickness on the order of one atomiclayer. The injected electrons needed for etching are able to tunnelthrough such a narrow potential well and recombine in the p++ bulkcrystal, which halts the etching reaction. The remnant etch rate in theetch-stop regime is attributed to the conduction band electrons, whosequantity is inversely proportional to the hole, i.e. boron,concentration. Four electrons are required to etch one silicon atom,which explains the dependence of the remnant etch rate on the fourthpower of the boron concentration.

[0037] It was observed that the formation of an SiO_(x) passivationlayer on p++ Si:B(2×10²⁰ cm⁻³) in aqueous KOH by in situ ellipsometricmeasurements. In the case of p⁺—Si, a large number of holes at thesurface causes spontaneous passivation with a thin oxide-like layer. Thelayer is not completely networked like thermal oxide, so it is etchedfaster and there is still transport of reactants and etch productsacross the layer, leading to some finite overall etch rate. The latticestrain induced by a high dopant concentration could enhance the layer'sgrowth. Furthermore, the etch rate reduction is not a Fermi-level effectsince the phenomenon is exhibited by both heavily doped p- andn-silicon.

[0038] Chen et al., J. Electrochem. Soc. 142, p.172 (1995), assimilatedthe observations and hypotheses above and their own findings into acomposite electrochemical model, where etch stopping is attributed tothe enhancement of the oxide film growth rate under high carrierconcentration. The key process is hole-driven oxidation at theinterface, which inhibits etching by competing with a reaction for Si—Sibonds and hydroxyl radicals, but more importantly, by building theSiO_(x) barrier. In p++ silicon, a sufficient quantity of holes foretch-stop behavior is supplied as the converse of the electron actionoutlined by Seidel et al. That is, instead of electrons thermallyescaping the potential well or tunneling through into the bulk crystal,holes from the bulk crystal thermally overcome or tunnel through thepotential barrier to the interface.

[0039] It will be appreciated that this etch-stop process is dynamic,i.e., it is a continuous competition of silicon dissolution andformation/dissolution of the oxide-like layer, whose net result is anonzero etch rate.

[0040] Germanium is appealing as an etch-resistant additive because itis isoelectronic to, and perfectly miscible in, silicon and diffusesmuch less readily than dopants and impurities in silicon. Furthermore,the epitaxy of silicon-germanium alloys is selective with respect tosilicon oxide, facilitating patterning and structuring, and even affordshigher carrier mobilities to electronics monolithically integrated withMEMS.

[0041] Existing germanium-based etch-stop systems are, at best, onlymarginally suitable for silicon micromachining. In spite of theaforementioned advantages to using germanium, currently there is aninadequate understanding of the etch-stop effect in silicon-germaniummaterials and no information on anisotropic etching of high germaniumcontent solid solutions.

[0042] Many isotropic etchants for pure germanium exist. Common to allof these is an oxidizer, such as HNO₃ or H₂O₂, and a complexing agent toremove the oxide, like HF or H₃PO₄. Early studies were made on isotropicgermanium etching by solutions such as “Superoxol”, a commerciallyavailable H₂O₂—HF recipe. More recently, investigations have been madeon various combinations of HNO₃, HNO₂, HF, H₂SO₄, H₂SO₂,CH₃COOH, H₂O₂,and H₂O.

[0043] In fact, some of these compositions selectively etch germanium orsilicon-germanium alloys over silicon, because of differences in therelative oxidation or oxide dissolution rates, but only one etchantexhibits the inverse preference relevant to this project: 100% NH₄OH at75° C. directly attacks polysilicon at 2.5 μm/hr but polygermanium atonly 660 Å/hr. Unfortunately, the selectivity is only about 37, the etchrate for silicon is impracticably slow, and the etch is isotropic, whichlimits its usefulness in micromachining.

[0044] Previous results with heavy concentrations of germanium insilicon are likewise discouraging with respect to siliconmicromachining. Shang et al., J. Electrochem. Soc. 141, p. 507 (1994),incorporated herein by reference, obtained a selectivity of 6 forrelaxed, dislocated Si_(0.7)Ge_(0.3):B (10¹⁹ cm⁻³) in aKOH-propanol-K₂Cr₂O₇ aqueous solution. Yi et al., Mat. Res. Soc. Symp.Proc. 3779, p. 91 (1995), developed a novel NH₄NO₃—NH₄OH etchant withselectivities better than 1000 at 70° C. for 10% and higher germaniumalloys. The mixture does not etch pure germanium, but etches puresilicon at 5.67 μm/hr, a weak pace for micromachining purposes. Bothsystems are isotropic.

[0045] By holding the Si_(0.7)Ge_(0.3):B film under the criticalthickness, Shang's team improved the selectivity in the sameKOH-propanol-K₂Cr₂O₇ solution to about 40. Narozny et al., IEEE IEDM(1988) 563, were the first to use such a “strain-selective” recipe, butonly realized a selectivity of 20 (for 30% germanium doped with 10¹⁸cm⁻³ boron) and a sluggish etch rate of 1.5 μm/hr at room temperaturefor pure silicon.²⁶ Although the results of Shang et al. and Narozny etal. might have simply been from the well-established etch-stop abilityof boron, Godbey et al., Appl. Phys. Lett. 56, p. 374 (1990), achieved aselectivity of 17 with undoped Si_(0.7)Ge_(0.3). None of the articles onstrain-selective etchants offer an explanation for the selectivity.

[0046] The anemic etch rate is a grave disadvantage because many MEMSstructures can be fairly large compared to typical VLSI dimensions.Moreover, MEMS structures subjected to strain-selective etchants wouldhave to be thinner than the critical thickness. However, as apseudomorphic structure is released and its strain relieved, theselectivity would deteriorate. A sacrificial strained etch-stop layercould be used, imposing additional process steps and design constraints,but would at least provide advantages over current oxide/nitridesacrificial layers: monocrystallinity can continue above the layer andsilicon-germanium's growth selectivity with respect to oxide addsdesign/patterning freedom.

[0047] The consensus of the research community has been that lowconcentrations of germanium have little or no effect on etch stopping inanisotropic etchants like KOH and EDP. Up to 12% germanium, Seidel etal. detected no significant suppression of etch rate. p++ layersstrain-compensated with 2% germanium showed no remarkable differencesfrom those without germanium. By implanting germanium, Feijóo et al., J.Electrochem. Soc.: 139, pp. 2312-13 (1992), attained a maximumselectivity of 12 to 24 in EDP at 80° C., corresponding to a dose with apeak concentration of about 0.6%.

[0048] Finne et al., J. Electrochem. Soc. 114, p.969 (1967), however,observed that Si_(1-x)Ge_(x) solid solutions with x as small as 0.05 didnot etch in an ethylenediamine-pyrocatechol-water (EPW) solution. Thisdiscrepancy may be attributed to the use of {111} wafers, where accuratemeasurements are difficult because etching in the <111> direction isvery slow. No other information has been reported on germanium-richalloys in anisotropic media. Corresponding to the ostensibleineffectiveness of germanium as an etch-stop agent in most publications,there has been little discussion of the source of the limitedselectivity that has been detected. Seidel et al. cautioned that theirmodel for heavily-doped boron etch stops is not applicable to germaniumbecause the element is isoelectronic to silicon. They assumed insteadthat the small reduction of the etch rate is either due to changes inthe energy band structure, or else a consequence of the extremely highconcentration of lattice defects such as misfit dislocations which couldact as recombination centers.

[0049] The invention provides a SiGe monocrystalline etch-stop materialsystem on a monocrystalline silicon substrate. The etch-stop materialsystem can vary in exact composition, but is a doped or undopedSi_(1-x)Ge_(x) alloy with x generally between 0.2 and 0.5. Across itsthickness, the etch-stop material itself is uniform in composition. Theetch stop is used for micromachining by aqueous anisotropic etchants ofsilicon such as potassium hydroxide, sodium hydroxide, lithiumhydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, andhydrazine. For example, a cantilever can be made of this etch-stopmaterial system, then released from its substrate and surroundingmaterial, i.e., “micromachined”, by exposure to one of these etchants.These solutions generally etch any silicon containing less than 7×10¹⁹cm⁻³ of boron or undoped Si_(1-x)Ge_(x), alloys with x less thanapproximately 18. Thus, it has been determined that alloying siliconwith moderate concentrations of germanium leads to excellent etchselectivities, i.e., differences in etch rate versus pure undopedsilicon. This is attributed to the change in energy band structure bythe addition of germanium. Furthermore, the nondegenerate doping in theSi_(1−x)Ge_(x) alloy should not affect the etch-stop behavior. Theetch-stop of the invention includes the use of a graded-compositionbuffer between the silicon substrate and the SiGe etch-stop material.Nominally, the buffer has a linearly-changing composition with respectto thickness, from pure silicon at the substrate/buffer interface to acomposition of germanium, and dopant if also present, at thebuffer/etch-stop interface which can still be etched at an appreciablerate. Here, there is a strategic jump in germanium and concentrationfrom the buffer side of the interface to the etch-stop material, suchthat the etch-stop layer is considerably more resistant to the etchant.For example, the buffer could grade up to Si_(0.5)Ge_(0.15), then jumpto a uniform etch-stop layer of Si_(0.7)Ge_(0.3). Nominally, thecomposition gradient in the buffer is 5-10% Ge/micron, and the jump inGe concentration is 5-15 relative atomic percent Ge. The buffer andetch-stop materials are deposited epitaxially on a standard siliconsubstrate, such as by chemical vapor deposition-(CVD) or molecular beamepitaxy (MBE). Note in the above example that the germaniumconcentration leads to etch stop behavior, and therefore dopingconcentrations in the etch stop can be varied independently, withoutaffecting etch selectivity.

[0050] With respect to the effect of crystalline defects on theetch-stop behavior, in accordance with the invention usingSi_(1-x)Ge_(x) alloys, the influence of defects is minimal. The use of agraded buffer suppresses the threading dislocation density (TDD) in thetop etch-stop layer, which leads to a uniform, nearly defect-freeSi_(1-x)Ge_(x) etch stop. The significance of the jump inconcentration(s) at the end of the graded region is that the part mustbe well defined and dimensions well controlled. Thus, a high selectivityshould exist between the top etch-stop layer and the end of the gradedregion for abrupt, predictable etch-stop behavior. A smoothcompositional transition from buffer to etch-stop layer would lead tocurved edges and greater dimensional variability in the micromachinedpart, whereas compositional jumps would yield clean, sharp edges andprecise dimensions in the released structure.

[0051] However, if the jump is too large, e.g., greater than ˜20-25atomic % Ge, the corresponding change in lattice constant, i.e., thelattice mismatch, would create defects.

[0052] The Si_(1-x)Ge_(x); etch-stop material system, which can besubstituted for heavily boron-diffused layers, broadens the spectrum ofavailable etch-stop materials, including undoped (isoelectronic)materials, thus improving the design flexibility for micromachinedstructures.

[0053] For example, standard micromachining processes limit thedimensions of silicon sensor structures to a single uniform thickness.Resonant devices for inertial sensing would benefit considerably frommore flexible design in which the resonators are thinner than theseismic mass. The invention provides an enabling technology for such amulti-thickness structure. Such a fundamental advantage makes the noveltechnology widely applicable to the fabrication of MEMS by siliconmicromachining.

[0054] A tremendously significant application is the ability tointegrate mechanical and electronic devices on the same material.Replacement of the heavily boron-doped etch stop, which is incompatiblewith integrated circuit (IC) requirements, by isoelectronic and/ormoderately-doped etch stops of device quality allows concurrentprocessing of mechanical devices and associated electronics on the samewafer. Germanium is perfectly miscible in silicon and diffuses much lessreadily than dopants and impurities. Alloying with germanium alsoaffords higher carrier mobilities to the electronic devices.

[0055] Furthermore, epitaxy of Si_(1-x)Ge_(x), alloys is selective withrespective to silicon oxide, which facilitates patterning andstructuring. In addition, defects do not seem to affect the etch-stopefficacy of these materials.

[0056] In developing the germanium-based etch stops of the invention,standard 3″ or 4″ phosphorous-doped (2-4 Ω·cm) or boron-doped (7-10.2Ω·cm) (001) silicon substrates were used. The wafers were cleaned for 10minutes in a piranha bath (3:1 95% H₂SO₄ in water: 30% H₂O₂ in water)and 10 seconds in 4.4% HF and DI water. The substrates were then left inthe load lock (˜10⁻⁸ Torr) of the vertical UHVCVD reactor overnight. Onthe following day, the substrates were raised to the lip of the reactorchamber for about two hours to drive off any volatiles, organics, andwater. Then the wafers were desorbed of whatever oxide remained byraising them into the 850-900° C. reactor chamber for several minutes. Asilicon buffer layer on the order of 1 μm was deposited with SiH₄ whilethe reactor was brought to process temperature. Following thispreparation procedure each time, the epitaxial structures were grown inthe temperature range 750-900° C. using SiH₄, GeH₄, 1% B₂H₆ in H₂, and1% PH₃ in H₂.

[0057] KOH and EDP were used in the etching. KOH is a commonly studiedetchant, the simplest and easiest to consider, and relatively easy andsafe to use. Although details of absolute etch rate differ, variousanisotropic silicon etchants have behaved consistently. Seidel et al.'swell-subscribed theory of anisotropic etching is explicitlyetchant-nonspecific. Results, discussions, and conclusions regardinganisotropic etching and etch-stopping of silicon are widely consideredto be valid for any anisotropic etchant. Cylindrical etching andpatterned oxide masks were both used to determine the efficacy of Geconcentration on etch rate.

[0058] To test the utility of the relaxed epitaxial SiGe etch stops,epitaxial structures were fabricated: WU_(—)2, WU_(—)3, WU_(—)4, andUHV_(—)17 as shown in FIGS. 1A-1D. FIG. 1A is a functional block diagramof an epitaxial SiGe etch stop structure 100 (WU_(—)2) configured on asilicon substrate 102. The structure includes a plurality of relaxedgraded layers 104 that vary from Si_(0.98)Ge_(0.02), 5×10²⁰ cm⁻¹ B atthe substrate surface, to the top surface layer of Si_(0.74)Ge_(0.26),10¹⁸ cm⁻³ P. The thickness of each layer are provided in sum.

[0059]FIG. 1B is a functional block diagram of an epitaxial SiGe etchstop structure 110 (WU_(—)3) configured on a silicon substrate 112. Thestructure includes a plurality of relaxed graded layers 114 that varyfrom Si_(0.99)Ge_(0.01) at the substrate surface, to the top surfacelayer of Si_(0.84)Ge_(0.16)

[0060]FIG. 1C is a functional block diagram of an epitaxial SiGe etchstop structure 120 (WU_(—)4) configured on a silicon substrate 122. Thestructure includes a relaxed graded layer 124 of Si_(0.66)Ge_(0.34).

[0061]FIG. 1D is a functional block diagram of an epitaxial SiGe etchstop structure 130 (WU_(—)4) configured on a silicon substrate 132. Thestructure includes a plurality of relaxed graded layers 134 that varyfrom Si_(0.97)Ge_(0.03), 3×10¹⁵ cm⁻³B at the substrate surface, to thetop surface layer of Si_(0.66)Ge_(0.34), 4×10¹⁶ cm⁻³ B.

[0062] The compositional grading is known to considerably relax thesuperficial epitaxial layer while effectively suppressing the TDD. Theslow grading rate and generous thickness of these epistructures assure awell-relaxed top film. Thus, the graded buffer enables etchingexperiments on relaxed, high quality, high germanium content alloys, anetching regime that has never been accessible before. As discussedheretofore, prior research dealt with pseudomorphic Si_(1-x)Ge_(x)layers or low concentrations of germanium to minimize dislocations, orheavy germanium alloys saturated with threading dislocations. Hence, thegrading technique permits one to use the intrinsic etch-stop propertiesof Si_(1-x)Ge_(x) solid solutions.

[0063] Based on the approximate volume of a cross-sectional TEM sample,a single threading dislocation in a TEM sample represents a TDD of about108 cm⁻². FIG. 2 is a cross-sectional TEM micrograph of structure 110(WU_(—)3). The top surface is in the upper right direction. The parallellines (misfit dislocations) define the graded buffer. No threadingdislocations can be found, which confirms high crystalline quality. Theblurred vertical bands are “bend contours”, an artifact of TEM, notthreading dislocations.

[0064] The absence of threading dislocations in FIG. 2 confirms thatstructures 110 (WU_(—)2), 120 (WU_(—)3), and 130 (UHV_(—)17), which wereprocessed in virtually identical fashion, contain very few defects. TDDsin such relaxed, graded structures have been shown to be in the range of10⁵-10⁶ cm⁻². By omitting the graded buffer, structure 120 (WU_(—)4) wasintentionally processed to be significantly imperfect, as verified byFIG. 3. FIG. 3 is a cross-sectional TEM micrograph of structure 120(WU_(—)4). The top surface is to the right. In contrast to FIG. 2, thisfilm is saturated with threading dislocations, which confirms poorcrystalline quality. The misfit dislocations in all four of thesesamples are buried under such a thick overlayer that they cannotpossibly affect etching from the top surface.

[0065] Dopant concentrations of structures 100 (WU_(—)2) and 130(UHV_(—)17) are shown in the graphs of FIGS. 4 and 5 respectively. Thedopant concentrations were calculated from the mobilities of puresilicon and pure germanium, as indicated. Since structure 130(UHV_(—)17) contains 30% germanium, the true boron content liessomewhere in between closer to the pure silicon line. Regardless, it isclear that the boron doping does not approach the levels needed for etchstopping. Structure 130 was doped p-type to investigate potentialinteractions or synergies with germanium that were suppressed instructure 100 by intentional background n-doping.

[0066] The characteristics of these materials (top layer) that arerelevant to etching are summarized in the following table. sample avg %Ge (EDX) doping [cm⁻³] defect density (TEM) WU_2 26 10¹⁸ P (SIMS) LowWU_3 17 None Low WU_4 34 None High UHV_17 30 4 × 10¹⁶ B (SRP) Low

[0067] Structure 100 (WU_(—)2) was used to identify the criticalgermanium concentration by cylindrically etching and to obtain etch ratevalues by etching from the top surface.

[0068] The cylindrical etch results of structure 100 (WU_(—)2), as shownin the graph of FIG. 6A, confirm the etch-stop behavior of germanium andnarrowed the threshold germanium concentration to the range of 16-22%.It was ensured that there were no effects from boron by doping the filmn-type. The terraces on the left of the graph, defined by the rounddots, represent the layers in the epistructure. The left scale reflectsthe depth of each layer while the right scale relates the nominalgermanium concentration of each layer. The arc is the initial groovesurface, and the square dots trace the etched surface.

[0069]FIG. 6B is a magnification of the left side of FIG. 6A. It isclear that the etch rate increases dramatically somewhere around 18-20%germanium, suggesting that the critical germanium concentration is inthat vicinity.

[0070] The cylindrical etch results of structure 130 (UHV_(—)17); asshown in the graph of FIG. 7, show the etch accelerating dramaticallyaround 4.8-5 μm depth. The 5% Ge/μm grading rate reasonably assures thatthe threshold germanium concentration is near 20% germanium. Theprofiles of each side of the groove are shown. The lower bar marks wherethe profile begins to deviate from the initial grooved shape. The depthof this point appears to be 4.8-5.0 μm below the top surface.

[0071] The results of the etch rate tests using oxide windows arepresented in the following table. wafer at % Ge concentration Ge [cm⁻³]etch rate [μm/hr] WU_2 25.6 1.28 × 10²² 0.070 WU_3 16.9 8.45 × 10²¹0.234 WU_4 34.0 1.70 × 10²² 0.040 UHV_17 30.0 1.50 × 10²² 0.133

[0072] The etch rate for <100> intrinsic silicon in 34% KOH at 60° C.was taken as 18.29 μm/hr from Seidel et al. The experimental data forstructures 100 (WU_(—)2), 110 (WU_(—)3), 120 (WU_(—)4), and 130(UHV_(—)17) are shown in the table. Normalized by 18.29 μm/hr, they areplotted in the graph of FIG. 8 along with Seidel et al.'s points.

[0073] Some features in FIG. 8 should be emphasized. First, there wasappreciably greater variability, both up and down, in the individualetch rates of “good” structure 120 (WU_(—)4) pieces than of the othergood samples, hence the error bar. A comparison of all the data supportsthe belief that the considerable surface roughness of structure 120(WU_(—)4), from lattice-mismatch stress and the high TDD, is probably toblame. Thus, the graded layer has already proven its efficacy since thegraded layer samples did not display this problem.

[0074] The shape of the new curve very closely resembles that ofEDP-boron curve, adding confidence in the new data as well as implyingthe existence of a universal: etch-stop model. In addition, KOH, a moreenvironmentally friendly etch stop than EDP, appears to be a better etchstop with SiGe alloy than EDP with the conventional p++ etch stop.

[0075] Despite the popular sentiment in the literature, it isindisputable that silicon-germanium alloys with sufficient germanium areexceptional etch stops that rival the most heavily boron-dopedmaterials. Three different etching techniques and two etchant systems,KOH and EDP, conclusively show this. The intersection of the steepportion of the KOH-germanium curve with unity relative etch rate, theso-called “critical concentration” as defined by Seidel et al., appearsto be 2×10²¹ cm⁻³, i.e., 4%, for germanium. Although this value is about100 times greater than their “critical concentration” for boron, higherselectivities can theoretically be attained with germanium because thereare neither solid solubility nor electrical activity limits.

[0076] The substantial selectivities obtained from the well-relaxed,low-defect sample structures 100 (WU_(—)2), 110 (WU_(—)3), and 130(UHV_(—)17) indicate that strain, induced by defects or dissimilaratomic radii, is not principally responsible for etch-stop behavior.

[0077] Defects do not play a central role in etch resistance. Theexcellent results from WU_(—)2, WU_(—)3, and UHV_(—)17, relaxedmaterials with low TDDs, controvert the speculation that lattice defectsserving as recombination centers cause the etch stop behavior withgermanium or isoelectronic additives, respectively. Furthermore, acomparison of the etch rate of structure 120 (WU_(—)4) to theKOH-germanium trendline indicates that even a high TDD does notinfluence etch stopping dramatically (if at all), nor in a predictablefashion.

[0078] The immediately attractive explanation for germanium's newfoundetch-stop potency in silicon is the mechanism outlined by R. Leancu,Sensors and Actuators, A 46-47 (1995) 35-37, incorporated herein byreference. For 15-30% germanium, it seems more logical to interpolatefrom the bulk properties of pure germanium than to postulate only howgermanium influences the properties of otherwise pure silicon. That is,one should give the germanium atom just as much credit as the siliconatom, since it is no longer a dopant, but rather an alloying species inthe truest sense. Thus, the silicon-germanium alloys in question shouldshow a palpable influence from the etching characteristics of puregermanium, which include a slow rate in KOH.

[0079] Keeping this simple chemistry approach in mind, a completelymiscible binary system like silicon-germanium would display a lineardependence of etch rate versus alloy composition. Even without etch ratedata at high germanium concentrations, including pure germanium, FIG. 8plainly illustrates that such is not the case. Along the same lines, itis unclear why there would be some critical concentration of germaniumfor an etch-stop effect if the etch rate is simply a consequence ofchemical structure, i.e., the proportion of each element. In fact, anonlinear plot and a critical concentration imply that the etch rate isa function of energy band structure rather than chemical structure.

[0080] On a related note, FIG. 8 shows that the germanium-KOH curve isremarkably similar in shape, but not necessarily slope, to the boron-EDPcurve, which ascribes its shape to the electronic etch-stop theory. Itis difficult to imagine that the germanium-KOH data would just happen toresemble the boron-EDP data, based on a completely different model thatwarns of no applicability to germanium. That is, it is highly improbablethat the true etch-stop mechanism for germanium is entirely unrelated tothe true mechanism for boron when the shapes agree so well.

[0081] There are reasons to consider an energy band model to account forthe etch-stop behavior in silicon-germanium solid solutions. First, theSi_(1-x)Ge_(x) data resemble the p++ Si:B data, including the criticalconcentration and power-law dependence of the remnant etch rate, and thep++ Si:B data is explained well by energy band effects. At thesequantities, germanium is known to markedly change the band structure ofsilicon. Furthermore, two possible mechanisms for the etch stop effectof germanium were defects and energy bands. Defect enhancedrecombination can be eliminated due to our graded layer approach. Energyband structure is the only other possibility.

[0082] Pure bulk germanium has an energy bandgap, E_(x), of 0.66 eV atroom temperature, compared to 1.12 eV for pure bulk silicon. Hence, theaddition of germanium to silicon reduces the bandgap: unstrainedSi_(0.7)Ge_(0.3), the situation for samples WU_(—)2, WU_(—)3, WU_(—)4,and UHV_(—)17, has an energy gap of approximately 1.04 eV. Germaniumalso has a smaller electron affinity, χ, than silicon, 4.00 eV versus4.05 eV. Thus, the incorporation of germanium decreases the electronaffinity as well. As germanium is added, the shrinking bandgap andelectron affinity reduce the band-bending, the potential well in theconduction band, and the potential barrier in the valence band.

[0083] The height of the potential barrier in the valence band, b, isgiven by: $\begin{matrix}{b = {\left( {\chi - d} \right) + {\frac{1}{2}E_{g}}}} & \lbrack 1\rbrack\end{matrix}$

[0084] for a generic intrinsic semiconductor, where d is the distance ofthe Fermi level from E=0, the reference vacuum level. It is understoodthat the bandgap of Si_(1-x)Ge_(x) does not change perfectly linearlywith germanium concentration, but it is not known how electron affinitydecreases with increasing germanium content. Nevertheless, if the twofunctions are approximated as linear, then b is also roughly linearlydependent on germanium concentration.

[0085] Adding germanium to intrinsic silicon also increases the amountof equilibrium electrons and holes, n_(i) and P_(i), respectively, viathe decreasing bandgap: $\begin{matrix}{n_{i} = {p_{i} = {\left( {N_{c}N_{v}} \right)^{\frac{1}{2}}{\exp \left( {- \frac{E_{g}}{2{kT}}} \right)}}}} & \lbrack 2\rbrack\end{matrix}$

[0086] where N_(c) and N_(v) are the effective density of states in theconduction and valence bands, respectively, k is Boltzmann's constant,and T is temperature. To simplify the description, N_(c) and N_(v) willbe assumed to be constant and equal to the values for pure silicon.Again, if Eg's dependence on germanium concentration is consideredlinear, then P_(i) is exponentially related to germanium concentration.

[0087] The increased pi increases the passivation reaction. For theintrinsic situation, it is assumed that the well/barrier is not sharpenough to allow tunneling. This is especially true for Si_(1-x)Ge_(x),with the shallower barrier. Furthermore, the inversion layer at thesurface is n-type.

[0088] Then the supply of holes to the passivation reaction is h, theamount of holes from the bulk that overcome the potential barrierthermally. Thus, h is a Boltzmann activated process: $\begin{matrix}{h = {p_{i}{\exp \left( {- \frac{b}{kT}} \right)}}} & \lbrack 3\rbrack\end{matrix}$

[0089] Since p_(i) is exponentially dependent on germanium content whileb is linearly related, h is overall exponentially related to germaniumconcentration. This can easily be seen by substituting expressions [1]and [2] into [3], yielding: $\begin{matrix}{h = {\left( {N_{c}N_{v}} \right)^{\underset{2}{T}}{\exp \begin{pmatrix}{{- E_{g}} - \chi + d} \\{1T}\end{pmatrix}}}} & \lbrack 4\rbrack\end{matrix}$

[0090] where E_(g) and χ are linearly dependent on germanium content. Ifa critical hole concentration exists for interrupting the etch process,then a critical germanium concentration will be observed.

[0091] The potential barrier in the valence band increases as the Fermilevel moves closer to the valence band, but the hole concentration issignificantly increased by p-doping. In fact, the two effects exactlyoffset each other. In the extrinsic case, the equilibrium holeconcentration, p, is defined as: $\begin{matrix}{p = {n_{i}{\exp \left( \frac{\frac{E_{g}}{2} - E_{F}}{kT} \right)}}} & \lbrack 5\rbrack\end{matrix}$

[0092] E_(g)/2-E_(F) is precisely the change in b when the material isdoped. Then, when expression [5] is substituted for p_(i) in equation[3], E_(g)/2-E_(F) exactly cancels the change in b in expression [3].

[0093] Thus, with nondegenerate doping, the value of h never changesfrom: $\begin{matrix}{h = {n_{i}{\exp \left( {- \frac{b_{i}}{kT}} \right)}}} & \lbrack 6\rbrack\end{matrix}$

[0094] where b_(i) is the height of the barrier in the intrinsicmaterial. Thus, a great advantage of the SiGe etch stop is that the etchselectivity depends only on Ge concentration.

[0095] Test structures of structure 110 (WU_(—)3), completely undopedmaterial, were fabricated and probed. The structure 110 (WU_(—)3) didnot provide the ‘hardest’ etch stop available with SiGe alloys becausethe germanium concentration (15-17%) was near the concentration whenetch stop selectivity starts to decrease. The results were verypromising as shown in FIG. 9.

[0096]FIG. 9 is a photograph of a top view of a micromachined proof mass900. Even at these low Ge concentrations, etched parts like the proofmass in FIG. 9 are possible. Higher Ge concentrations in the uniformlayer (30%) result in extremely hard etch stops, with selectivitiesapproaching 1000:1.

[0097] It is apparent from cylindrical and top surface etching with EDPand KOH and actual structures micromachined in EDP that relaxedsilicon-germanium alloys with sufficient germanium are exceptional etchstops. Selectivities as high as 1000, corresponding to 34% germanium,have been obtained in KOH for the <100>direction. Neither strain nordefects are responsible for these results. High defect density does notinfluence the etch rate of Si_(1-x)Ge_(x); dramatically. A plot ofrelative etch rate versus germanium concentration follows the same shapeas p++ Si:B data, including a critical concentration and a power-lawdependence of the remnant rate. The etch stop behavior in relaxed SiGealloys is correlated to changes in band structure, which are solelyconnected to Ge concentration.

[0098] The extremely high etch selectivities achieved with the SiGe etchstop material system of the invention have immediate applications informing semiconductor/oxide structures. One method of forming silicon oninsulator is to bond a Si wafer to another Si wafer that is coated withsilicon dioxide. If one of the wafers is thinned, then a thin layer ofSi on silicon dioxide/Si is created. Such structures are useful in lowpower electronics and high speed electronics since the Si active layeris isolated from a bulk Si substrate via the silicon dioxide layer. Themain disadvantage of this process is the difficulty in thinning one sideof the silicon substrate-silicon dioxide-silicon substrate sandwich. Inorder to have high reproducibility and high yield, the entire wafer mustbe thinned uniformly and very accurately. Buried etch stops have beenused with little success. Even buried, thin layers of strained SiGe havebeen used, but as mentioned earlier these etch demonstrate etchselectivities <<100, and therefore are not sufficient.

[0099] The relaxed SiGe alloys of the invention are ideally suited forthis type of etch stop. By bonding a structure 1000 of a graded SiGelayer 1004 and a uniform composition layer 1006 on a silicon wafer 1002to a structure 1008 having a silicon wafer 1010 coated with silicondioxide 1012, the etch-stop of the invention can be used to create avery uniform relaxed SiGe alloy on silicon dioxide, which in turn is ona silicon wafer. This process is shown schematically in FIG. 10.

[0100] Once the structures are bonded through, for example, annealing,the silicon substrate 1002 and graded layer 1004 are selectively etchedaway. The finished structure 1014 is a SiGe-on-insulator substrate. Itwill be appreciated that the structure 1008 can also be a bulkinsulating material, such as glass or a glass ceramic.

[0101] An entire new materials system from which to make highlyeffective etch stops has been developed. The new system offers manyadvantages over current technologies. Germanium is isoelectronic to andperfectly soluble in silicon, and hardly diffuses in it. The depositionof silicon-germanium is selective with respect to oxide. Defects do notweaken the etch-stop efficacy. The etch-stop material can be completelyundoped, and according to the proposed band structure model,nondegenerate doping does not influence the etch-stop behavior. Thisaffords incredible utility and design flexibility, especially tointegration with microelectronics. To this end, germanium would evenafford higher carrier mobilities.

[0102] In fact, this etch stop system can easily be used to integratevarious strained Si electronics on relaxed SiGe on any desired substrate(eg, insulating or semiconductor substrates), where one such system isSiGe on insulator (SiGeOI). More details of this procedure are providedin the following description. The main approaches for the fabrication ofsemiconductors on insulator are separation-by-implanted-oxygen (SIMOX)and wafer bonding (followed by etch-back or Smart-Cut). SIMOX involvesimplantation by oxygen followed by a high temperature anneal, and henceis attractive due to its apparent simplicity. This technique has shownsome success for low Ge compositions, but for higher Ge fractions, inparticular for Si_(0.5)Ge_(0.5), the buried oxide structure was notdemonstrated, due to the thermodynamic instability of Si_(1-x)Ge_(x)O₂.Simply stated, Ge is not incorporated into the oxide, due to thevolatile nature of GeO₂, and therefore for high Ge fractions, there areinsufficient Si atoms to form a stable oxide. On the other hand, thebonding technique, which involves the bonding of a SiGe wafer to anoxidized handle wafer followed by the removal of excess material, can beapplied to any Ge fraction, without the problem of an unstable oxide. Inaddition, the procedure is general, one can create SiGe on any desiredsubstrate, including any insulating wafer.

[0103] The process flow for the bond/etch-back SiGeOI fabricationtechnique is shown schematically in FIGS. 11A-11F. The process isseparated into growth: (a) UHVCVD growth of relaxed SiGe graded bufferfollowed by CMP, (b) re-growth of strained Si (ε-Si) and SiGe bondinglayer, and bond/etch-back steps: (c) wafer bonding to insulatingsubstrate, (d) backside grinding, (e) Si etch stopping in the gradedlayer, (f) SiGe etch stopping on the strained Si.

[0104] During the first growth, a relaxed 2.5 μm compositionally gradedSiGe buffer 1102, capped with 2 μM of Si_(0.75)Ge_(0.25) was depositedonto a Si substrate 1100 at 900° C. using a UHVCVD reactor. The gradedbuffer minimizes threading dislocations and ensures that misfit are onlypresent in the graded layers and not in the uniform composition cap, butthese underlying misfits still generate strain fields which cause theformation of surface cross-hatch during growth. To eliminate thissurface roughness, which would hinder wafer bonding, the wafer waspolished (using chemical-mechanical polishing, CMP) until thecross-hatch was no longer visible using Nomarsky microscopy.

[0105] Next a strained i structure 1104, consisting of 12 nm of strainedSi, followed by a layer 1106 of 150 nm of Si_(0.75)Ge_(0.25), was grownat 650° C. via UHVCVD onto the polished SiGe wafers.

[0106] The low growth temperature ensures minimal surface exchange andinter-diffusion, and hence guarantees a sharp interface between the Siand SiGe layers. The strained Si layer acts as an etch stop during thefinal etch step, and depending on the thickness requirement and surfaceroughness constraint for the strained Si channel, may possibly also beused as a MOSFET device channel.

[0107] The SiGe wafer was then bonded to a thermally oxidized Si wafer1108, with an oxide layer 1110 thickness of 200 nm. To ensure adequatebonding, a hydrophobic pre-bonding clean was performed on the wafers.The standard RCA clean cannot be employed for this purpose since the SC1bath etches Ge and hence roughens the SiGe surface. Instead, a piranhaclean (10 minutes) followed by a 50:1 HF dip (30 seconds) was used,which leaves the surface hydrophobic. Such a clean was found to lead tostronger bonding than hydrophilic cleans, after subsequent annealing atmoderate temperatures. In addition, the wafers must also be bonded in anultra-clean environment to ensure no intrinsic voids (as shown in the IRimage in FIG. 12A) due to particles at the wafer interfaces.

[0108] The wafer pair was annealed for 2 hours at 800° C. in a nitrogenambient. The moderate temperature ensures strong bonding, but is lowenough to minimize the diffusion of Ge into the strained Si layer. Inaddition, the 2 hour anneal at this temperature allows the intrinsichydrogen voids formed during initial annealing to diffuse. The resultingpair was found to be void free using infrared imaging, and the fracturesurface energy deduced with the Maszara razor test technique (FIG. 13B)was 3.7 J/m² (which is similar to the surface fracture energy found forSi to oxide bonding), demonstrating that the bonding is indeed strongenough to undergo further material processing, without the risk ofdelamination.

[0109] After bonding the wafers, the pair was coated with nitride toprotect the backside of the handle wafer during etching. The backside ofthe SiGe wafer was then ground as at 1112, removing approximately 450μm, and a first etch as at 1114 was performed on the wafers to removethe remaining Si from the SiGe wafers. Any etch which attacks Si and notSiGe can be used (eg, KOH, TMAH). For example, a KOH mixture (30% KOH byweight in water) at 80° C., with an etching time of 2 hours can beemployed to remove the backside Si from the SiGe wafer. KOH etches donot significantly attack relaxed Si_(1-x)Ge_(x), with Ge compositions ofroughly 20% or higher, and hence stop near the top of the grade in ourbuffers. Note here that unlike pure Si, or strained SiGe basedstructures, the relaxed SiGe layer provides a natural etch stop, thusalleviating the need for a p⁺⁺ stop layer. This flexibility of doping asan independent variable with respect to etch-stop capability isimportant in designing device layers for different applications. Forexample, p⁺⁺ layers are not desired in RF applications.

[0110] The next etch 1116 was employed to remove the remaining SiGe, andstop on the strained Si layer 1104. The active ingredient of this etchconsists of any Ge oxidizing agent (eg, H₂O₂, HNO₃, low temperature wetoxidation), combined with an oxide stripping agent (eg, HF). Forexample, a low temperature (650° C.-750° C.) wet oxidation has beenfound to oxidize SiGe at much faster rates than Si, as shown in FIG. 13;for a 1 hour oxidation at 700° C., Si₀₇₅Ge₀₂₅ oxidizes at a rate of 2.5nm/min, whereas Si has an oxidation rate of roughly 100 times smaller.In combination with a subsequent HF dip, the above oxidation can be usedto remove very thin layers of SiGe, while stopping on Si.

[0111] A chemical alternative to the above, is a solution ofHF:H₂O₂:CH₃COOH (1:2:3), with an etch time of approximately 30 minutes(in the case when the Si etch stops near the 20% Ge region). This hasbeen shown to etch SiGe preferentially, with a very high selectivity; inparticular, for relaxed Si_(0.75)Ge_(0.25) versus Si, the selectivity isroughly 300. For demonstration purposes, a test sample consisting of 400nm relaxed Si_(0.75)Ge_(0.25) on 12 nm strained Si was partially maskedand the etch depth versus time was measured using a profilometer. Theresults in FIG. 14 clearly show the high selectivity, in addition to therelatively fast etch rate of the Si_(0.75)Ge_(0.25) surface layer. Animportant observation is that the solution was found to etch dislocationthreads on the strained Si stop layer preferentially, causing pitting,which in turn lead to breeches in the strained Si layer when the etchtime was prolonged.

[0112]FIG. 15 shows a TEM cross-sectional image of the SiGeOI structurefabricated using the proposed technique. No structural defects, such asthreading dislocations, were observed in the cross-sectional TEM of theSiGe layer. A low density of threads in the 10⁵ cm⁻² range was confirmedvia EPD (etch pit density) of both the as-grown and bonded SiGe, whichproves that there is no substantial increase in threading dislocationsdue to the proposed process. This is in contrast to SIMOX, which canpossibly introduce many additional defects depending on the materialsystem being implanted. In particular, the threading dislocation forimplanted SiGe of various Ge fractions has not yet been reported in theliterature.

[0113] An AFM scan of the strained Si surface after the final etching,is shown in FIG. 16. The rms roughness was found to be roughly 1.0 nm,with a maximum peak-to-valley difference of 6.4 nm. This demonstratesthat although the HF:H₂O₂:CH₃COOH (1:2:3) SiGe etch, has a goodselectivity, it leaves the strained Si layer moderately rough. Hence,when using this etch, the Si etch stop layer might not be smooth enoughto double as a device channel, since the surface roughness may affectdevice performance. If this is so, the easiest and most general approachsimply requires the removal of the Si etch stop layer with KOH, or anyanother Si etch that is selective to the Ge composition being used. Thedesired device structure can then be grown onto the SiGeOI substrate,including a strained Si surface channel or any other more elaboratestructure.

[0114] An alternative approach, especially in the case of buried channeldevices, would involve the incorporation of the device channel layersinto the bonding structure. Either avenue is easily attainable using ourflexible bonding/etch-back process. Using this general approach, thebenefits of an insulating substrate (or for that matter, any substrate)can easily be applied to any SiGe device, without any constraints onSiGe thickness, Ge composition or insulating layer thickness or type.

[0115] Although the present invention has been shown and described withrespect to several preferred embodiments thereof, various changes,omissions and additions to the form and detail thereof, may be madetherein, without departing from the spirit and scope of the invention.

What is claimed is:
 1. A monocrystalline etch-stop layer system for useon a monocrystalline Si substrate, said system comprising asubstantially relaxed graded layer of Si_(1-x)Ge_(x), and a uniformetch-stop layer of substantially relaxed Si_(1-y)Ge_(y).
 2. The systemof claim 1, wherein x<0.20.
 3. The system of claim 1, wherein y>0.19. 4.The system of claim 1, wherein x<0.20 and y>0.19.
 5. The system of claim1, wherein said Si_(1-y)Ge_(y) layer is bonded to a second substrate. 6.The system of claim 5, wherein said second substrate comprises Si. 7.The system of claim 5, wherein said second substrate comprises glass. 8.The system of claim 5., wherein said second substrate comprises quartz.9. The system of claim 5, wherein said second substrate comprises alayer of SiO₂ on a second Si substrate.
 10. The system of claim 5,wherein the first Si substrate and graded layer are substantiallyremoved.
 11. The system of claim 6, wherein the first Si substrate andgraded layer are substantially removed.
 12. The system of claim 7,wherein the first Si substrate and graded layer are substantiallyremoved.
 13. The system of claim 8, wherein the first Si substrate andgraded layer are substantially removed.
 14. The system of claim 9,wherein the first Si substrate and graded layer are substantiallyremoved.
 15. The system of claim 1, wherein a SiO₂ layer is depositedonto said Si_(1-y)Ge_(y) layer.
 16. The system of claim 15, wherein saidSiO₂ layer is bonded to a second substrate.
 17. The system of claim 16,wherein said second substrate comprises a layer of SiO₂ on a second Sisubstrate.
 18. The system of claim 16, wherein said second substratecomprises a layer of SiO₂ on a glass substrate.
 19. The system of claim16, wherein said second substrate comprises a layer of SiO₂ on a quartzsubstrate.
 20. The system of claim 16, wherein the first Si substrateand graded layer are substantially removed.
 21. The system of claim 17,wherein the first Si substrate and graded layer are substantiallyremoved.
 22. The system of claim 18, wherein the first Si substrate andgraded layer are substantially removed.
 23. The system of claim 19,wherein the first Si substrate and graded layer are substantiallyremoved.
 24. The system of claim 10, wherein the surface is planarized.25. The system of claim 11, wherein the surface is planarized.
 26. Thesystem of claim 12, wherein the surface is planarized.
 27. The system ofclaim 13, wherein the surface is planarized.
 28. The system of claim 14,wherein the surface is planarized.
 29. The system of claim 20, whereinthe surface is planarized.
 30. The system of claim 21, wherein thesurface is planarized.
 31. The system of claim 22, wherein the surfaceis planarized.
 32. The system of claim 23, wherein the surface isplanarized.
 33. A monocrystalline etch-stop layer system for use on amonocrystalline Si substrate, said system comprising a substantiallyrelaxed graded layer of Si_(1-x)Ge_(x)a uniform etch-stop layer ofsubstantially relaxed Si_(1-y)Ge_(y); and a strained Si_(1-z)Ge_(z)layer.
 34. The system of claim 0.33, wherein z<y.
 35. The system ofclaim 33, wherein y>0.18.
 36. The system of claim 33, wherein y>0.18 andz<y.
 37. The system of claim 33, wherein y>0.18 and z=0.
 38. The systemof claim 33, wherein said Si_(1-x)Ge_(x) is bonded to a secondsubstrate.
 39. The system of claim 38, wherein said second substratecomprises Si.
 40. The system of claim 38, wherein said second substratecomprises glass.
 41. The system of claim 38, wherein said secondsubstrate comprises quartz.
 42. The system of claim 38, wherein saidsecond substrate comprises a layer of SiO₂ on a second Si substrate. 43.The system of claim 38, wherein the first Si substrate and graded layerare substantially removed.
 44. The system of claim 39, wherein the firstSi substrate and graded layer are substantially removed.
 45. The systemof claim 40, wherein the first Si substrate and graded layer aresubstantially removed.
 46. The system of claim 41, wherein the first Sisubstrate and graded layer are substantially removed.
 47. The system ofclaim 42, wherein the first Si substrate and graded layer aresubstantially removed.
 48. The structure in claim 33 in which a SiO₂layer is deposited onto said Si_(1-x)Ge_(x) layer.
 49. The system ofclaim 48, wherein said SiO₂ layer is bonded to a second substrate. 50.The system of claim 49, wherein the second substrate comprises a layerof SiO₂ on a second Si substrate.
 51. The system of claim 49, whereinthe second substrate comprises a layer of SiO₂ on a glass substrate. 52.The system of claim 49, wherein the second substrate comprises a layerof SiO₂ on a quartz substrate.
 53. The system of claim 49, wherein thefirst Si substrate and graded layer are substantially removed.
 54. Thesystem of claim 50, wherein the first Si substrate and graded layer aresubstantially removed.
 55. The system of claim 51, wherein the first Sisubstrate and graded layer are substantially removed.
 56. The system ofclaim 52, wherein the first Si substrate and graded layer aresubstantially removed.
 57. A monocrystalline etch-stop layer system foruse on a monocrystalline Si substrate, comprising a substantiallyrelaxed graded layer of Si_(1-x)Ge_(x); a uniform etch-stop layer ofsubstantially relaxed Si_(1-y)Ge_(y); a second etch-stop layer ofstrained Si_(1-z)Ge_(z); and a substantially relaxed Si_(1-w)Ge_(w)layer.
 58. The system of claim 57, wherein y−0.05<w<y+0.05.
 59. Thesystem of claim 57, wherein w=y.
 60. The system of claim 57, whereinsaid Si_(1-w)Ge_(w) is bonded to a second substrate.
 61. The system ofclaim 60, wherein said second substrate comprises Si.
 62. The system ofclaim 60, wherein said second substrate comprises glass.
 63. The systemof claim 60, wherein said second substrate comprises quartz.
 64. Thesystem of claim 60, wherein said second substrate comprises a layer ofSiO₂ on a second Si substrate.
 65. The system of claim 60, wherein thefirst Si substrate and graded layer are substantially removed.
 66. Thesystem of claim 61, wherein the first Si substrate and graded layer aresubstantially removed.
 67. The system of claim 62, wherein the first Sisubstrate and graded layer are substantially removed.
 68. The system ofclaim 63, wherein the first Si substrate and graded layer aresubstantially removed.
 69. The system of claim 64, wherein the first Sisubstrate and graded layer are substantially removed.
 70. The system ofclaim 57, wherein a SiO₂ layer is deposited onto said Si_(1-w)Ge_(w)layer.
 71. The system of claim 70, wherein said SiO₂ layer is bonded toa second substrate.
 72. The system of claim 70, wherein the secondsubstrate comprises a layer of SiO₂ on a second Si substrate.
 73. Thesystem of claim 70, wherein the second substrate comprises a layer ofSiO₂ on a glass substrate.
 74. The system of claim 70, wherein thesecond substrate comprises a layer of SiO₂ on a quartz substrate. 75.The system of claim 70, wherein the first Si substrate and graded layerare substantially removed.
 76. The system of claim 71, wherein the firstSi substrate and graded layer are substantially removed.
 77. The systemof claim 72, wherein the first Si substrate and graded layer aresubstantially removed.
 78. The system of claim 73, wherein the first Sisubstrate and graded layer are substantially removed.
 79. The system ofclaim 74, wherein the first Si substrate and graded layer aresubstantially removed.
 80. A method of integrating a device or layercomprising: depositing a substantially relaxed graded layer ofSi_(1-x)Ge_(x); on a Si substrate; depositing a uniform etch-stop layerof substantially relaxed Si_(1-y)Ge_(y) on said graded buffer; andetching portions of said substrate and said graded buffer in order torelease said etch-stop layer.
 81. The method of claim 80, whereinx<0.20.
 82. The method of claim 80, wherein y>0.19.
 83. The method ofclaim 80, wherein x<0.20 and y>0.19.
 84. The method of claim 80, whereinthe etchant used to release the etch-stop layer is KOH.
 85. The methodof claim 80, wherein the etchant used to release the etch-stop layer isTMAH.
 86. The method of claim. 80, wherein the etchant used to releasethe etch-stop layer is EDP.
 87. The method of claim 80, wherein theetch-stop is released and the etch-stop layer is planarized.
 88. Themethod of claim 87, wherein the method of planarization ischemical-mechanical polishing (CMP).
 89. A method of integrating adevice or layer comprising: depositing a substantially relaxed gradedlayer of Si_(1-x)Ge_(x) on a Si substrate; depositing a uniform firstetch-stop layer of substantially relaxed Si_(1-y)Ge_(y) on said gradedbuffer; depositing a second etch-stop layer of strained Si_(1-x)Ge_(x);depositing a substantially relaxed Si_(1-w)Ge_(w) layer; etchingportions of said substrate and said graded buffer in order to releasesaid first etch-stop layer; and etching portions of said residual gradedbuffer in order to release the second etch-stop Si_(1-z)Ge_(z) layer.90. The method of claim 89, wherein the etchant used to release thesecond etch-stop layer comprises an oxidant and an oxide strippingagent.
 91. The method of claim 90, wherein the oxidant oxidizes Ge muchmore rapidly than Si.
 92. The method of claim 90, wherein the oxidantcomprises H₂O₂.
 93. The method of claim 90, wherein the stripping agentcomprises HF.
 94. The method of claim 90, wherein the oxidant comprisesH₂O₂ and the stripping agent comprises HF.
 95. The method of claim 94,wherein the diluting agent comprises CH₃COOH.
 96. The method of claim95, wherein the ratio of chemicals in the etchant are (1:2:3) for(HF:H₂O₂:CH₃COOH).
 97. The method of claim 89, wherein wet oxidation isused to selectively oxidize the Si_(1-x)Ge_(x); and Si, thereby actingas an etch-stop with respect to Si_(1-y)Ge_(y).
 98. The method of claim97, wherein the wet oxidation temperature is <750 degrees Celsius. 99.The method of claim 97, wherein the oxidized layers are removed by an HFand water solution.
 100. The method of claim 98, wherein the oxidizedlayers are removed by an HF solution.
 101. The method of claim 90,wherein the Si_(1-z)Ge_(z) layer is subsequently removed using aselective etchant with respect to the Si_(1-w)Ge_(w) layer.
 102. Themethod of claim 91, wherein the Si_(1-z)Ge_(z) layer is subsequentlyremoved using a selective etchant with respect to the Si_(1-w)Ge_(w)layer.
 103. The method of claim 92, wherein the Si_(1-z)Ge_(z) layer issubsequently removed using a selective etchant with respect to theSi_(1-w)Ge_(w) layer.
 104. The method of claim 93, wherein theSi_(1-z)Ge_(z) layer is subsequently removed using a selective etchantwith respect to the Si_(w)Ge_(w) layer.
 105. The method of claim 94,wherein the Si_(1-z)Ge_(z), layer is subsequently removed using aselective etchant with respect to the Si_(1-w)Ge_(w) layer.
 106. Themethod of claim 95, wherein the Si_(1-z)Ge_(z) layer is subsequentlyremoved using a selective etchant with respect to the Si_(1-w)Ge_(w)layer.
 107. The method of claim 96, wherein the Si_(1-z)Ge_(z), layer issubsequently removed using a selective etchant with respect to theSi_(1-w)Ge_(w) layer.
 108. The method of claim 97, wherein theSi_(1-z)Ge_(z) layer is subsequently removed using a selective etchantwith respect to the Si_(1-w)Ge_(w) layer.
 109. The method of claim 98,wherein the Si_(1-z)Ge_(z) layer is subsequently removed using aselective etchant with respect to the Si_(1-w)Ge_(w) layer.
 110. Themethod of claim 99, wherein the Si_(1-z)Ge_(z) layer is subsequentlyremoved using a selective etchant with respect to the Si_(1-w)Ge_(w)layer.
 111. The method of claim 100, wherein the Si_(1-z)Ge_(z) layer issubsequently removed using a selective etchant with respect to theSi_(1-w)Ge_(w) layer.
 112. (New) A semiconductor structure comprising: alayer structure including a uniform etch-stop layer, wherein saiduniform etch-stop layer has a relative etch rate which is less thanapproximately the relative etch rate of Si doped with 7×10¹⁹ boronatoms/cm^(3.)
 113. (New) The semiconductor structure of claim 112,wherein the uniform etch-stop layer is substantially relaxed.
 114. (New)The semiconductor structure of claim 113, wherein the uniform etch-stoplayer comprises Si_(1-y)Ge_(y).
 115. (New) The semiconductor structureof claim 114, wherein y>0.19.
 116. (New) The semiconductor structure ofclaim 113, wherein the uniform etch-stop layer comprises a silicondioxide layer.
 117. (New) The semiconductor structure of claim 113,wherein a surface of the uniform etch-stop layer is planarized. 118.(New) The semiconductor structure of claim 112, wherein the layerstructure comprises a strained layer disposed over the uniform etch stoplayer.
 119. (New) The semiconductor structure of claim 118, wherein thestrained layer comprises Si_(1-z)Ge_(z) and 0≦z<1.
 120. (New) Thesemiconductor structure of claim 118, further comprising: an insulatorlayer disposed over the layer structure.
 121. (New) The semiconductorstructure of claim 112, further comprising: a handle wafer, wherein thelayer structure is bonded to the handle wafer.
 122. (New) The structureof claim 121, wherein the handle wafer comprises an insulator. 123.(New) The semiconductor structure of claim 121, wherein the handle wafercomprises a material selected from the group consisting of silicon,glass, quartz, and silicon dioxide.
 124. (New) The semiconductorstructure of claim 123, wherein the handle wafer comprises a silicondioxide layer.
 125. (New) The semiconductor structure of claim 112,wherein the layer structure comprises a substantially relaxed layer.126. (New) The semiconductor structure of claim 125, wherein the relaxedlayer is graded.
 127. (New) The semiconductor structure of claim 126,wherein the relaxed layer comprises Si_(1-x)Ge_(x).
 128. (New) Thesemiconductor structure of claim 127, wherein x<0.2.
 129. (New) Thesemiconductor structure of claim 128, wherein the uniform etch-stoplayer comprises substantially relaxed Si_(1-y)Ge_(y) and y>0.19. 130.(New) The semiconductor structure of claim 125, wherein thesubstantially relaxed layer is disposed over the uniform etch-stoplayer.
 131. (New) The semiconductor structure of claim 130, furthercomprising: a semiconductor substrate disposed over the relaxed layer.132. (New) The semiconductor structure of claim 125, wherein thesubstantially relaxed layer is disposed under the uniform etch-stoplayer.
 133. (New) The semiconductor structure of claim 132, wherein thelayer structure comprises a first strained layer disposed over theuniform etch-stop layer.
 134. (New) The semiconductor structure of claim132, wherein the first strained layer comprises Si_(1-z)Ge_(z) and0≦z<1.
 135. (New) A semiconductor structure, comprising: a layerstructure including a strained Si_(1-z)Ge_(z) layer, and a handle wafercomprising an insulator, the layer structure being bonded to the handlewafer, wherein 0<z<1.
 136. (New) The semiconductor structure of claim135, wherein z=0.
 137. (New) The semiconductor structure of claim 135,wherein the layer structure includes a substantially relaxed uniformetch-stop layer, the strained Si_(1-z)Ge_(z) layer is disposed over theuniform etch-stop layer, 0≦z<1, and the uniform etch-stop layer has arelative etch rate which is less than approximately the relative etchrate of Si doped with 7×10¹⁹ boron atoms/cm³.
 138. (New) Thesemiconductor structure of claim 137, wherein the etch-stop layercomprises substantially relaxed Si_(1-y)Ge_(y).
 139. (New) Thesemiconductor structure of claim 137, wherein the layer structurecomprises a substantially relaxed layer and the uniform etch-stop layeris disposed over the substantially relaxed layer.
 140. (New) Thesemiconductor structure of claim 139, wherein the substantially relaxedlayer comprises graded Si_(1-x)Ge_(x).
 141. (New) The structure of claim139, further comprising: an insulator layer disposed over the layerstructure.
 142. (New) The semiconductor structure of claim 139, whereinthe layer structure comprises a substantially relaxed graded layerdisposed over the substantially relaxed layer.
 143. (New) Thesemiconductor structure of claim 142, wherein the substantially relaxedgraded layer comprises Si_(1-x)Ge_(x).
 144. (New) A semiconductorstructure, comprising: a layer structure including: a uniform etch-stoplayer; and a strained layer disposed over the uniform etch-stop layer,and an insulator layer disposed over the layer structure, wherein theuniform etch-stop layer has a relative etch rate which is less thanapproximately the relative etch rate of Si doped with 7×10¹⁹ boronatoms/cm³.
 145. (New) The semiconductor structure of claim 144, whereinthe etch-stop layer comprises substantially relaxed Si_(1-y)Ge_(y). 146.(New) The semiconductor structure of claim 144, wherein the strainedlayer comprises Si_(1-z)Ge_(z) and 0≦z<1.
 147. (New) A semiconductorstructure, comprising: an etch-stop layer; and a substantially relaxedlayer disposed over the etch-stop layer.
 148. (New) The semiconductorstructure of claim 147, wherein the etch-stop layer comprises strainedSi_(1-z)Ge_(z), and 0≦z<1.
 149. (New) The semiconductor structure ofclaim 148, wherein z=0.
 150. (New) The semiconductor structure of claim147, wherein the substantially relaxed layer comprises Si_(1-w)Ge_(w).151. (New) A semiconductor structure, comprising: a first uniformetch-stop layer; a second etch-stop layer disposed over the uniformetch-stop layer; and a substantially relaxed layer disposed over thesecond etch-stop layer, wherein the first uniform etch-stop layer has arelative etch rate which is less than approximately the relative etchrate of Si doped with 7×10¹⁹ boron atoms/cm^(3.)
 152. (New) Thesemiconductor structure of claim 151, wherein the first uniformetch-stop layer comprises substantially relaxed Si_(1-y)Ge_(y). 153.(New) The semiconductor structure of claim 151, wherein the secondetch-stop layer comprises strained Si_(1-z)Ge_(z).
 154. (New) Thestructure of claim 153, wherein 0≦z<1.
 155. (New) The semiconductorstructure of claim 154, wherein z=0.
 156. (New) The semiconductorstructure of claim 151, wherein the substantially relaxed layercomprises Si_(1-w)Ge_(w).
 157. (New) The semiconductor structure ofclaim 151, further comprising: a handle wafer comprising an insulator,wherein the substantially relaxed layer is bonded to the handle wafer.158. (New) The semiconductor structure of claim 157, wherein the handlewafer comprises a material selected from the group consisting ofsilicon, glass, quartz, and silicon dioxide.
 159. (New) Thesemiconductor structure of claim 157, further comprising: an insulatorlayer disposed over the strained layer.
 160. (New) The semiconductorstructure of claim 151, further comprising: a substantially relaxedgraded layer, wherein the first uniform etch-stop layer is disposed overthe graded layer.
 161. (New) The semiconductor structure of claim 160,wherein the substantially relaxed graded layer comprises Si_(1-x)Ge_(x).162. (New) The semiconductor structure of claim 160, further comprising:a first substrate, wherein the substantially relaxed graded layer isdisposed on the first substrate.
 163. (New) A method for forming asemiconductor structure, the method comprising: forming a uniformetch-stop layer; providing a handle wafer; and bonding the uniformetch-stop layer to the handle wafer, wherein said uniform etch-stoplayer has a relative etch rate which is less than approximately therelative etch rate of Si doped with 7×10¹⁹ boron atoms/cm³.
 164. (New)The method of claim 163, wherein the uniform etch-stop layer comprisessubstantially relaxed Si_(1-y)Ge_(y).
 165. (New) The method of claim163, further comprising: planarizing a surface of the uniform etch-stoplayer prior to bonding.
 166. (New) The method of claim 163, furthercomprising: forming a substantially relaxed graded layer before formingthe uniform etch-stop layer, wherein the uniform etch-stop layer isformed over the substantially relaxed graded layer.
 167. (New) Themethod of claim 166, wherein the relaxed graded layer comprisesSi_(1-x)Ge_(x).
 168. (New) The method of claim 166, further comprising:releasing the etch-stop layer by removing at least a portion of thegraded layer.
 169. (New) The method of claim 166, wherein releasing theetch-stop layer comprises a wet etch.
 170. (New) The method of claim166, further comprising: providing a semiconductor substrate, whereinthe substantially relaxed graded layer is formed over the semiconductorsubstrate.
 171. (New) A method for forming a semiconductor structure,the method comprising: providing a first substrate; and forming a layerstructure over the first substrate by: forming a uniform etch-stop layerover the first substrate; and forming a strained layer over the uniformetch-stop layer, wherein the uniform etch-stop layer has a relative etchrate which is less than approximately the relative etch rate of Si dopedwith 7×10¹⁹ boron atoms/cm³.
 172. (New) The method of claim 171, whereinthe etch-stop layer comprises substantially relaxed Si_(1-y)Ge_(y). 173.(New) The method of claim 171, wherein the strained layer comprisesSi_(1-z)Ge_(z) and 0≦z<1.
 174. (New) The method of claim 171, furthercomprising: providing a second substrate comprising an insulator; andbonding the layer structure to the second substrate.
 175. (New) Themethod of claim 174, wherein the second substrate comprises a materialselected from the group consisting of silicon, glass, quartz, andsilicon dioxide.
 176. (New) The method of claim 171, further comprising:forming an insulator layer over the strained layer.
 177. (New) Themethod of claim 171, further comprising: releasing the strained layer byremoving at least a portion of the uniform etch-stop layer.
 178. (New)The method of claim 177, wherein releasing the strained layer comprisesa wet etch.
 179. (New) The method of claim 171, wherein forming thelayer structure comprises forming a substantially relaxed graded layerand the uniform etch-stop layer is formed over the graded layer. 180.(New) The method of claim 179, wherein the graded layer comprisesSi_(1-x)Ge_(x).
 181. (New) The method of claim 179, further comprising:releasing the strained layer by removing at least a portion of thegraded layer and at least a portion of the uniform etch-stop layer. 182.(New) The method of claim 181, wherein releasing the strained layercomprises a wet etch.
 183. (New) A method for forming a semiconductorstructure, the method comprising: forming a layer structure by forming astrained Si_(1-z)Ge_(z) layer, and bonding the layer structure to ahandle wafer comprising an insulator, wherein 0≦z<1.
 184. (New) Themethod of claim 183, wherein z=0.
 185. (New) The method of claim 183,wherein forming the layer structure comprises forming a uniformetch-stop layer, the strained Si_(1-x)Ge_(x) layer is formed over theuniform etch-stop layer, and the uniform etch-stop layer has a relativeetch rate which is less than approximately the relative etch rate of Sidoped with 7×10¹⁹ boron atoms/cm³.
 186. (New) The method of claim 185,wherein the uniform etch-stop layer comprises substantially relaxedSi_(1-y)Ge_(y).
 187. (New) The method of claim 185, further comprising:forming an insulator layer over the layer structure.
 188. (New) Themethod of claim 185, further comprising: releasing the strained layer byremoving at least a portion of the uniform etch-stop layer.
 189. (New)The method of claim 188, wherein releasing the strained layer comprisesa wet etch.
 190. (New) The method of claim 185, wherein forming thelayer structure comprises forming a substantially relaxed graded layer,and the uniform etch-stop layer is formed over the substantially gradedlayer.
 191. (New) The method of claim 190, wherein the relaxed gradedlayer comprises Si_(1-x)Ge_(x).
 192. (New) The method of claim 190,further comprising: releasing the strained layer by removing at least aportion of the graded layer and at least a portion of the uniformetch-stop layer.
 193. (New) The method of claim 192, wherein releasingthe strained layer comprises a wet etch.
 194. (New) The method of claim190, further comprising: forming an insulator layer over the layerstructure.
 195. (New) The method of claim 190, further comprising:providing a substrate, wherein the layer structure is formed over thesubstrate.
 196. (New) The method of claim 195, further comprising:releasing the strained layer by removing at least a portion of thesubstrate, at least a portion of the graded layer, and at least aportion of the uniform etch-stop layer.
 197. (New) The method of claim196, wherein releasing the strained layer comprises a wet etch. 198.(New) A method for forming a semiconductor structure, the methodcomprising: forming a strained etch-stop layer; and forming asubstantially relaxed Si_(1-w)Ge_(w) layer over the etch-stop layer.199. (New) The method of claim 198, wherein the etch-stop layercomprises Si_(1-z)Ge_(z) and wherein 0≦z<1.
 200. (New) The method ofclaim 199, wherein z=0.
 201. (New) A method for forming a semiconductorstructure, the method comprising: forming a first uniform etch-stoplayer; forming a second etch-stop layer over the uniform etch-stoplayer; and forming a substantially relaxed layer over the secondetch-stop layer, wherein the first uniform etch-stop layer has arelative etch rate which is less than approximately the relative etchrate of Si doped with 7×10¹⁹ boron atoms/cm³.
 202. (New) The method ofclaim 201, wherein the first etch-stop layer comprises substantiallyrelaxed Si_(1-y)Ge_(y).
 203. (New) The method of claim 201, wherein thesecond etch-stop layer comprises strained Si_(1-z)Ge_(z) and 0≦z<1. 204.(New) The method of claim 203, wherein z=O.
 205. (New) The method ofclaim 201, wherein the substantially relaxed layer comprisesSi_(1-w)Ge_(w).
 206. (New) The method of claim 201, further comprising:bonding the substantially relaxed layer to a substrate comprising aninsulator.
 207. (New) The method of claim 206, wherein the substratecomprises a material selected from the group consisting of silicon,glass, quartz, and silicon dioxide.
 208. (New) The method of claim 206,further comprising: releasing the second etch-stop layer by removing atleast a portion of the first etch-stop layer.
 209. (New) The method ofclaim 208, wherein releasing the second etch-stop layer comprises a wetetch.
 210. (New) The method of claim 208, further comprising: releasingthe substantially relaxed layer by removing at least a portion of thesecond etch-stop layer.
 211. (New) The method of claim 208, whereinreleasing the substantially relaxed layer comprises a wet etch. 212.(New) The method of claim 201, further comprising: forming asubstantially relaxed graded layer, wherein the first uniform etch-stoplayer is formed on the graded layer.
 213. (New) The method of claim 212,wherein the substantially relaxed graded layer comprises Si_(1-x)Ge_(x).214. (New) The method of claim 212, further comprising: bonding thesubstantially relaxed layer to a substrate comprising an insulator. 215.(New) The method of claim 212, further comprising: releasing the firstetch-stop layer by removing at least a portion of the relaxed gradedlayer.
 216. (New) The method of claim 215, wherein releasing the firstetch-stop layer comprises a wet etch.
 217. (New) The method of claim215, further comprising: releasing the second etch-stop layer byremoving at least a portion of the first etch-stop layer.
 218. (New) Themethod of claim 215, wherein releasing the second etch-stop layercomprises a wet etch.
 219. (New) The method of claim 217, furthercomprising: releasing the relaxed layer by removing at least a portionof the second etch-stop layer.
 220. (New) The method of claim 219,wherein releasing the relaxed layer comprises a wet etch.
 221. (New) Themethod of claim 201, further comprising: providing a first substrate;and forming a layer structure over the first substrate by: forming asubstantially relaxed graded layer over the first substrate; wherein thefirst uniform etch-stop layer is formed over the graded layer, and thelayer structure comprises the substantially relaxed graded layer, thefirst uniform etch-stop layer, the second etch-stop layer, and thesubstantially relaxed layer.
 222. (New) The method of claim 221, whereinthe substantially relaxed graded layer comprises Si_(1-x)Ge_(x). 223.(New) The method of claim 221, wherein the first uniform etch-stop layercomprises substantially relaxed Si_(1-y)Ge_(y), the second etch-stoplayer comprises strained Si_(1-z)Ge_(z)0≦z<1, and the substantiallyrelaxed layer comprises Si_(1-w)Ge_(w).
 224. (New) The method of claim221, further comprising: bonding the layer structure to a secondsubstrate including an insulator.
 225. (New) The method of claim 224,wherein the second substrate comprises a material selected from thegroup consisting of silicon, glass, quartz, and silicon dioxide. 226.(New) The method of claim 221, the method further comprising: releasingthe first etch-stop layer by removing at least a portion of the firstsubstrate and at least a portion of the graded layer; and releasing thesecond etch-stop layer by removing at least a portion of the firstetch-stop layer.
 227. (New) The method of claim 226, further comprising:bonding the layer structure to a second substrate prior to releasing thefirst etch-stop layer.
 228. (New) The method of claim 226, furthercomprising: releasing at least a portion of the relaxed layer byremoving at least a portion of the second etch-stop layer.
 229. (New) Amethod for forming a semiconductor structure, the method comprising:providing a first substrate; forming a layer structure on the firstsubstrate by: forming a substantially relaxed graded layer on the firstsubstrate; and forming a uniform etch-stop layer on the graded layer;and releasing the etch-stop layer by removing at least a portion of thesubstrate and at least a portion of the graded layer,